CPC H04B 1/71635 (2013.01) [G01S 13/0209 (2013.01); H04W 72/0446 (2013.01)] | 20 Claims |
1. An electronic device comprising:
a communication circuit configured to support ultra wideband (UWB) communication; and
at least one processor operatively connected to the communication circuit,
wherein the at least one processor is configured to control to:
transmit, to an external electronic device, a first packet including first information related to transmission of a second packet through the communication circuit in a slot duration of a slot, the slot duration corresponding to a transmission time of the first packet, and
transmit, to the external electronic device, at least one or more second packets corresponding to the first information through the communication circuit in a slot duration of a slot, the slot duration corresponding to a transmission time of the second packet,
wherein the first packet is a scrambled timestamp sequence (STS) packet configuration (SP) frame including a payload, and
wherein at least one or more second packets is an SP frame that does not include a frame payload.
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