US 12,074,615 B2
Error correction
Marco Sforzin, Cernusco Sul Naviglio (IT); Paolo Amato, Treviglio (IT); and Yang Lu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 20, 2022, as Appl. No. 17/969,856.
Claims priority of provisional application 63/348,438, filed on Jun. 2, 2022.
Prior Publication US 2023/0396272 A1, Dec. 7, 2023
Int. Cl. H03M 13/15 (2006.01); G06F 13/42 (2006.01); H03M 13/09 (2006.01)
CPC H03M 13/152 (2013.01) [G06F 13/4221 (2013.01); H03M 13/095 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die;
communicating the plurality of pairs of bits of the MTB from the LK die to the IF die via the plurality of LDIO lines;
responsive to a failure of one of the plurality of LDIO lines, performing a Bose-Chaudhuri-Hocquenghem (BCH) error correction on the pairs of bits mapped to the failed LDIO line, wherein each of the plurality of pairs of bits is a respective symbol for the BCH error correction;
mapping a different plurality of pairs of bits of the MTB to a different plurality of LDIO lines coupling a different LK die to a different IF die;
communicating the different plurality of pairs of bits of the MTB from the different LK die to the different IF die via the different plurality of LDIO lines; and
responsive to a failure of one of the different plurality of LDIO lines, performing the BCH error correction on the pairs of bits mapped to the failed different LDIO line, wherein each of the different plurality of pairs of bits is a respective symbol of the BCH error correction.