US 12,074,605 B2
Time interleaving circuit having glitch mitigation
Aradhana Kumari, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Jan. 6, 2023, as Appl. No. 18/151,332.
Claims priority of provisional application 63/299,831, filed on Jan. 14, 2022.
Prior Publication US 2023/0231546 A1, Jul. 20, 2023
Int. Cl. H03K 5/1252 (2006.01); H03K 5/135 (2006.01)
CPC H03K 5/1252 (2013.01) [H03K 5/135 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first loading stage configured to:
output first data representative of first serialized data;
a second loading stage configured to:
generate second serialized data;
receive the first data;
in response to the first data having a first state,
invert the second serialized data to generate second data representative of the second serialized data; and
output the second data; and
in response to the first data having a second state, output the second data without inverting the second serialized data; and
exclusive disjunction logic configured to:
receive the first and second data; and
operate on the first data and the second data to generate output data.