US 12,074,603 B1
Leakage-free dummy cell for semiconductor devices
Yu-Jheng Ou-Yang, Hsinchu (TW); Chi-Lin Liu, New Taipei (TW); Shang-Chih Hsieh, Taoyuan (TW); Wei-Hsiang Ma, Taipei (TW); and Kai-Chi Huang, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on May 8, 2023, as Appl. No. 18/313,384.
Int. Cl. H03K 3/037 (2006.01); H03K 3/3562 (2006.01)
CPC H03K 3/0372 (2013.01) [H03K 3/0375 (2013.01); H03K 3/35625 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a multiplexer, configured to output an inverse of an input data signal or an inverse of a scan input signal according to a scan enable signal;
a master latch, coupled to an output terminal of the multiplexer, and configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state; and
a slave latch, coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and configured to receive the input data signal and to output a latched slave latch data based on the input clock signal,
wherein a leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.