CPC H03K 21/10 (2013.01) [G06F 1/08 (2013.01); G06F 1/10 (2013.01)] | 20 Claims |
1. A device comprising:
clock controller circuitry including a first clock output, a second clock output, and a system clock output;
real-time clock (RTC) circuitry including a first clock input, a second clock input, and an RTC output, the first clock input coupled to the first clock output, the second clock input coupled to the second clock output; and
a system timer coupled to the clock controller circuitry and the RTC circuitry, the system timer including:
clock divider circuitry including a third clock input, a divider input, and a divider output, the third clock input coupled to the system clock output;
counter circuitry including a counter input and a counter output, the counter input coupled to the divider output;
comparison circuitry including a first input, a second input, and a comparison output, the first input coupled to the counter output, the second input configured to be coupled to the RTC output based on the second clock output; and
controller circuitry including an error input and a divider output, the error input configured to be coupled to the comparison output, the divider output coupled to the divider input.
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