US 12,074,599 B2
3D stacked integrated circuits having failure management
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 16, 2021, as Appl. No. 17/349,136.
Application 17/349,136 is a continuation of application No. 16/846,597, filed on Apr. 13, 2020, granted, now 11,043,952.
Application 16/846,597 is a continuation of application No. 16/218,889, filed on Dec. 13, 2018, granted, now 10,666,264, issued on May 26, 2020.
Prior Publication US 2021/0313990 A1, Oct. 7, 2021
Int. Cl. H03K 19/17756 (2020.01); G11C 16/04 (2006.01); H01L 27/06 (2006.01); H03K 17/687 (2006.01); H03K 19/0948 (2006.01); H03K 19/17704 (2020.01); H03K 19/17764 (2020.01); H10B 41/40 (2023.01); H10B 63/00 (2023.01)
CPC H03K 19/17756 (2013.01) [G11C 16/0483 (2013.01); H01L 27/0688 (2013.01); H03K 17/687 (2013.01); H03K 19/0948 (2013.01); H03K 19/17704 (2013.01); H03K 19/17764 (2013.01); H10B 41/40 (2023.02); H10B 63/30 (2023.02)] 29 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a plurality of integrated circuit dies configured in a stack, wherein memory cells and logic circuits are formed on the plurality of integrated circuit dies, wherein the stack is partitioned into a plurality of columns that are perpendicular to the plurality of integrated circuit dies; and
routes configurable to bypass at least a part of a respective column in the plurality of columns and re-route functionality of the respective column to at least a part of a different column of the plurality of columns.