US 12,074,598 B2
Level shifter enable
Srinivasan Ramarajan, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 23, 2022, as Appl. No. 18/146,282.
Application 18/146,282 is a division of application No. 17/373,061, filed on Jul. 12, 2021, granted, now 11,539,367.
Application 17/373,061 is a division of application No. 16/563,248, filed on Sep. 6, 2019, granted, now 11,063,593, issued on Jul. 13, 2021.
Claims priority of provisional application 62/753,545, filed on Oct. 31, 2018.
Prior Publication US 2023/0208422 A1, Jun. 29, 2023
Int. Cl. H03K 19/0185 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01); H03K 19/00 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 3/037 (2013.01); H03K 3/356113 (2013.01); H03K 19/0016 (2013.01); H03K 19/018528 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A level shifter circuit, comprising:
an enable signal inverter configured to receive a first power supply voltage and having an input terminal and an output terminal;
a data bus having a plurality of data lines;
a plurality of level shifters, each connected to the output terminal of the enable signal inverter and a respective one of the plurality of data lines, the plurality of level shifters configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain;
a level shifter enable circuit comprising:
a plurality of first control transistors, each of the first control transistors having a source connected to a ground terminal, a gate connected to the output terminal of the enable signal inverter, and a drain connected to a respective one of a plurality of level shifters;
a plurality of second control transistors, each of the second control transistors having a source connected to the ground terminal, a gate connected to the output terminal of the enable signal inverter, and a drain connected to the respective one of the plurality of level shifters; and
a third control transistor having a source configured to receive the first power supply voltage, a gate connected to the output terminal of the enable signal inverter, and a drain connected to a level shift inverter of each of the plurality of level shifters.