CPC H03K 19/018521 (2013.01) [H03K 3/037 (2013.01); H03K 3/356113 (2013.01); H03K 19/0016 (2013.01); H03K 19/018528 (2013.01)] | 20 Claims |
1. A level shifter circuit, comprising:
an enable signal inverter configured to receive a first power supply voltage and having an input terminal and an output terminal;
a data bus having a plurality of data lines;
a plurality of level shifters, each connected to the output terminal of the enable signal inverter and a respective one of the plurality of data lines, the plurality of level shifters configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain;
a level shifter enable circuit comprising:
a plurality of first control transistors, each of the first control transistors having a source connected to a ground terminal, a gate connected to the output terminal of the enable signal inverter, and a drain connected to a respective one of a plurality of level shifters;
a plurality of second control transistors, each of the second control transistors having a source connected to the ground terminal, a gate connected to the output terminal of the enable signal inverter, and a drain connected to the respective one of the plurality of level shifters; and
a third control transistor having a source configured to receive the first power supply voltage, a gate connected to the output terminal of the enable signal inverter, and a drain connected to a level shift inverter of each of the plurality of level shifters.
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