US 12,074,597 B2
Fail-safe protection architecture for high voltage tolerant input/output circuit
Kailash Kumar, Hazaribagh (IN); Prateek Singh, Noida (IN); and Akhil Thotli, Madanapalle (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Aug. 31, 2022, as Appl. No. 17/900,427.
Prior Publication US 2024/0072803 A1, Feb. 29, 2024
Int. Cl. H03K 19/007 (2006.01); H03K 19/003 (2006.01)
CPC H03K 19/007 (2013.01) [H03K 19/00384 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit of a chip, comprising:
an I/O circuit comprising a transistor connected to an I/O pad, wherein the I/O pad is connected to one or more other chips via an I/O bus;
a supply and failsafe detector component comprising:
a first input connected to an I/O supply voltage of the chip,
a second input connected to the I/O pad and receiving an I/O pad voltage as supply,
an I/O supply output signal generated by the supply and failsafe detector component, the I/O supply output signal having a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high voltage value when the I/O supply voltage of the chip is above the medium voltage level, wherein the medium voltage level is above a threshold voltage of the transistor of the I/O circuit and below the high voltage value; and
a multiplexer controlled by the I/O supply output signal, the multiplexer providing a reference voltage as input to the transistor of the I/O circuit.