CPC H03K 17/102 (2013.01) [G06F 30/31 (2020.01)] | 20 Claims |
1. A differential multiplexer comprising at least first and second input stages, each input stage comprising:
a first transistor receiving an input signal;
a second transistor receiving an inverse of the input signal;
a biasing circuit adapted to bias a gate terminal of each of the first and second transistors;
a first capacitor coupled to the biasing circuit and the gate terminal of the first transistor;
a second capacitor coupled to the biasing circuit and the gate terminal of the second transistor;
a first current source coupled between a source terminal of each of the first and second transistors and a ground terminal;
a first switch adapted to couple a drain terminal of the first transistor to a first terminal of a first resistor in response to a select signal, wherein a second terminal of the first resistor is coupled to a supply voltage;
a second switch adapted to couple a drain terminal of the second transistor to a first terminal of a second resistor in response to the select signal, wherein a second terminal of the second resistor is coupled to the supply voltage;
a third switch adapted to couple the drain terminal of the first transistor to the supply voltage in response to an inverse of the select signal; and
a fourth switch adapted to couple the drain terminal of the second transistor to the supply voltage in response to the inverse of the select signal.
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