US 12,074,568 B2
Multi-core oscillator with enhanced mode robustness
Hongrui Wang, San Jose, CA (US); and Abbas Komijani, Mountain View, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 9, 2022, as Appl. No. 17/941,767.
Application 17/941,767 is a continuation of application No. 17/730,721, filed on Apr. 27, 2022, granted, now 11,824,498.
Claims priority of provisional application 63/245,470, filed on Sep. 17, 2021.
Prior Publication US 2023/0093529 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03B 5/12 (2006.01); H03L 7/089 (2006.01); H03L 7/093 (2006.01)
CPC H03B 5/1228 (2013.01) [H03B 5/1243 (2013.01); H03L 7/0891 (2013.01); H03L 7/093 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A voltage-controlled oscillator comprising:
a core comprising a positive terminal and a negative terminal;
a first gain booster coupled to the positive terminal, the first gain booster comprising a first set of transconductance cells coupled end to end via a first disable transistor that is configured to be disabled when the core is in an in-phase operating mode; and
a second gain booster coupled to the negative terminal, the second gain booster comprising a second set of transconductance cells coupled end to end via a second disable transistor that is configured to be enabled when the core is in the in-phase operating mode.