US 12,074,545 B2
Semiconductor device and motor drive system
Kazuya Kobayashi, Yokohama Kanagawa (JP); and Hiroshi Odawara, Yokohama Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Sep. 1, 2022, as Appl. No. 17/901,318.
Claims priority of application No. 2022-048510 (JP), filed on Mar. 24, 2022.
Prior Publication US 2023/0308037 A1, Sep. 28, 2023
Int. Cl. G01R 31/42 (2006.01); H02P 23/14 (2006.01)
CPC H02P 23/14 (2013.01) 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first terminal connected to a first switch;
a second terminal connected to a second switch;
a third terminal connected to a third switch;
a fourth terminal connected to a fourth switch;
an amplification circuit including a first input end connectable to the first terminal across the first switch and connectable to the third terminal across the third switch, a second input end connectable to the second terminal across the second switch and connectable to the fourth terminal across the fourth switch, and an output end;
a fifth terminal to which the output end of the amplification circuit is connected; and
a switching circuit configured to:
switch the semiconductor device to a first state by putting each of the first and second switches in a connected state and putting each of the third and fourth switches in a non-connected state, wherein in the first state, the first input end is connected to the first terminal and insulated from the third terminal and the second input end is connected to the second terminal and insulated from the fourth terminal, and
switch the semiconductor device to a second state by putting each of the first and second switches in the non-connected state and putting each of the third and fourth switches in the connected state, wherein in the second state, the first input end is connected to the third terminal and insulated from the first terminal and the second input end is connected to the fourth terminal and insulated from the second terminal.