US 12,074,258 B2
Light emitting diode chip and method for manufacturing the same, display device
Lizhen Zhang, Beijing (CN); Guangcai Yuan, Beijing (CN); Qi Yao, Beijing (CN); and Mingxing Wang, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on May 27, 2021, as Appl. No. 17/332,852.
Claims priority of application No. 202011099277.6 (CN), filed on Oct. 14, 2020.
Prior Publication US 2022/0115562 A1, Apr. 14, 2022
Int. Cl. H01L 33/38 (2010.01); H01L 27/15 (2006.01); H01L 33/00 (2010.01); H01L 33/12 (2010.01); H01L 33/62 (2010.01)
CPC H01L 33/382 (2013.01) [H01L 27/156 (2013.01); H01L 33/005 (2013.01); H01L 33/12 (2013.01); H01L 33/62 (2013.01); H01L 2933/0016 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A display device, comprising a light emitting diode chip, wherein the light emitting diode chip comprises:
a light emitting functional layer comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked, and the second semiconductor layer comprises a plurality of second semiconductor patterns which are arranged at intervals;
a first electrode layer comprising a first electrode pattern electrically coupled to the first semiconductor layer; and
a second electrode layer disposed on a side, away from the light emitting layer, of the second semiconductor layer and comprising a plurality of second electrode patterns in one-to-one correspondence with the second semiconductor patterns, and the second electrode patterns are electrically coupled to the second semiconductor patterns correspondingly,
wherein the first electrode pattern is disposed on a side surface of the first semiconductor layer, so that an orthographic projection of the first electrode pattern on a plane in which the first semiconductor layer is located is at least partially not overlapped with the first semiconductor layer,
the display device further comprises: a driving substrate;
the driving substrate comprises a driving functional layer and a pixel defining layer, wherein the driving functional layer comprises a plurality of first coupling terminals, the pixel defining layer defines a plurality of pixel accommodating holes, and each of the pixel accommodating holes corresponds to more than one light emitting diode chips,
more than one of the first coupling terminals are disposed in each of the pixel accommodating holes, and each of the light emitting diode chips is flip-mounted in a corresponding one of the pixel accommodating holes, and the second electrode patterns are electrically coupled to the first coupling terminals in the corresponding one of the pixel accommodating holes,
wherein at least a part of the first electrode pattern protrudes from a side of the pixel accommodating hole away from the driving functional layer,
for the light emitting diode chips corresponding to any one pixel accommodating hole, first electrode patterns of adjacent ones of the light emitting diode chips are in contact with each other,
the pixel accommodating hole is configured with at least one second coupling terminal disposed on a side of the pixel defining layer away from the driving functional layer, the second coupling terminal being electrically coupled to a corresponding signal line in the driving functional layer, and
for the light emitting diode chips corresponding to any one pixel accommodating hole, the first electrode pattern of at least one light emitting diode chip disposed on an outermost side is electrically coupled to the second coupling terminal corresponding to the pixel accommodating hole.