US 12,074,224 B2
Semiconductor device and manufacturing method thereof
Yoshinobu Asami, Kanagawa (JP); Yutaka Okazaki, Kanagawa (JP); Satoru Okamoto, Kanagawa (JP); and Shinya Sasagawa, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Feb. 3, 2022, as Appl. No. 17/591,690.
Application 17/591,690 is a continuation of application No. 16/378,622, filed on Apr. 9, 2019, granted, now 11,245,039.
Application 16/378,622 is a continuation of application No. 15/959,548, filed on Apr. 23, 2018, abandoned.
Application 15/959,548 is a continuation of application No. 14/995,562, filed on Jan. 14, 2016, granted, now 9,954,112, issued on Apr. 24, 2018.
Claims priority of application No. 2015-012713 (JP), filed on Jan. 26, 2015; application No. 2015-012718 (JP), filed on Jan. 26, 2015; application No. 2015-039161 (JP), filed on Feb. 27, 2015; application No. 2015-041682 (JP), filed on Mar. 3, 2015; application No. 2015-046870 (JP), filed on Mar. 10, 2015; and application No. 2015-053100 (JP), filed on Mar. 17, 2015.
Prior Publication US 2022/0199831 A1, Jun. 23, 2022
Int. Cl. H01L 29/786 (2006.01); C23C 16/40 (2006.01); C23C 16/455 (2006.01); H01L 21/475 (2006.01); H01L 21/4757 (2006.01); H01L 21/67 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01)
CPC H01L 29/7869 (2013.01) [C23C 16/40 (2013.01); C23C 16/45531 (2013.01); H01L 21/475 (2013.01); H01L 21/47573 (2013.01); H01L 21/67207 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 29/0649 (2013.01); H01L 29/41733 (2013.01); H01L 29/42356 (2013.01); H01L 29/42376 (2013.01); H01L 29/42384 (2013.01); H01L 29/66969 (2013.01); H01L 29/78603 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/0262 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a transistor,
wherein the transistor comprises:
a first insulating layer;
an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer overlapping with a first region of the first insulating layer;
a second insulating layer disposed over the first insulating layer and the oxide semiconductor layer, the second insulating layer having a groove on the channel formation region;
a gate insulating layer formed along an inner wall of the groove; and
a gate electrode embedded in an inner side of the groove with the gate insulating layer provided therebetween,
wherein in a cross-section of a channel length direction of the transistor,
a length of a top surface of the gate electrode is larger than a length of a bottom surface of the gate electrode,
a side surface of the gate electrode in the inner side of the groove includes a first portion having a first taper angle and a second portion located under the first portion and having a second taper angle,
a degree of the first taper angle is different from a degree of the second taper angle,
a top surface of the second insulating layer, a top surface of the gate insulating layer, and the top surface of the gate electrode are polished surfaces flatted on a same plane, and
the second insulating layer has a region being in contact with a second region of the first insulating layer.