US 12,074,223 B2
Semiconductor device
Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Feb. 23, 2021, as Appl. No. 17/182,270.
Application 17/182,270 is a continuation of application No. 16/277,108, filed on Feb. 15, 2019, granted, now 11,094,830.
Application 16/277,108 is a continuation of application No. 15/820,575, filed on Nov. 22, 2017, granted, now 10,211,345, issued on Feb. 19, 2019.
Application 15/820,575 is a continuation of application No. 15/040,092, filed on Feb. 10, 2016, granted, now 9,831,351, issued on Nov. 28, 2017.
Application 15/040,092 is a continuation of application No. 14/028,776, filed on Sep. 17, 2013, granted, now 9,269,821, issued on Feb. 23, 2016.
Claims priority of application No. 2012-210230 (JP), filed on Sep. 24, 2012.
Prior Publication US 2021/0226060 A1, Jul. 22, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 29/1054 (2013.01); H01L 29/78696 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor including silicon in a channel formation region;
an insulating film over the first transistor;
a second transistor over the insulating film, the second transistor including an oxide semiconductor layer, a source electrode, a drain electrode, and a gate electrode; and
a protective insulating film over the gate electrode,
wherein the oxide semiconductor layer includes a first layer, a second layer over the first layer, and a third layer over the second layer,
wherein an energy gap of the second layer is smaller than an energy gap of the first layer,
wherein an energy gap of the third layer is larger than an energy gap of the second layer,
wherein a conductive layer is in contact with the source electrode or the drain electrode through a first opening opened in the protective insulating film in a channel length direction,
wherein the conductive layer is in contact with a gate electrode of the first transistor through a second opening opened in the protective insulating film and a third opening opened in the insulating film in a channel width direction, and
wherein part of the conductive layer is exposed.