US 12,074,220 B2
Formation of semiconductor arrangement comprising semiconductor column
Georgios Vellianitis, Haverlee (BE)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed on May 16, 2022, as Appl. No. 17/745,106.
Application 15/342,380 is a division of application No. 14/318,753, filed on Jun. 30, 2014, granted, now 9,490,331, issued on Nov. 8, 2016.
Application 17/745,106 is a continuation of application No. 15/342,380, filed on Nov. 3, 2016, granted, now 11,335,811.
Prior Publication US 2022/0271172 A1, Aug. 25, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/778 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 29/78618 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823885 (2013.01); H01L 27/092 (2013.01); H01L 29/41741 (2013.01); H01L 29/42392 (2013.01); H01L 29/66356 (2013.01); H01L 29/66666 (2013.01); H01L 29/7391 (2013.01); H01L 29/7788 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); H01L 21/823487 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor arrangement, comprising:
forming a buffer layer;
forming a first dielectric layer over the buffer layer;
forming a first opening in the first dielectric layer, wherein the buffer layer is exposed through the first opening; and
forming a first semiconductor column in the first opening, wherein the first semiconductor column extends above a top surface of the first dielectric layer; and
removing the first dielectric layer after forming the first semiconductor column.