| CPC H01L 29/785 (2013.01) [H01L 21/02362 (2013.01); H01L 21/76832 (2013.01); H01L 21/823431 (2013.01); H01L 23/5226 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01)] | 20 Claims |
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1. A semiconductor device structure, comprising:
a conductive gate stack formed over a substrate;
a gate dielectric layer covering opposite sidewalls and a bottom of the conductive gate stack;
a first gate spacer layer and a second gate spacer layer respectively covering portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack;
a source/drain contact structure separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer;
a first insulating capping feature covering the conductive gate stack, wherein the first insulating capping feature is adjacent to the gate dielectric layer and spaced apart from the second gate spacer layer by the gate dielectric layer; and
a second insulating capping feature covering the source/drain contact structure, wherein an upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.
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