US 12,074,215 B2
Semiconductor device and semiconductor device manufacturing method
Tomomi Yamanobe, Miyazaki (JP); Yoshinobu Takeshita, Miyazaki (JP); Kazutaka Kodama, Miyazaki (JP); and Minako Oritu, Miyazaki (JP)
Assigned to LAPIS SEMICONDUCTOR CO., LTD., Kanagawa (JP)
Filed by LAPIS SEMICONDUCTOR CO., LTD., Kanagawa (JP)
Filed on Aug. 8, 2023, as Appl. No. 18/231,377.
Application 18/231,377 is a division of application No. 16/280,250, filed on Feb. 20, 2019, granted, now 11,764,294.
Claims priority of application No. 2018-029528 (JP), filed on Feb. 22, 2018.
Prior Publication US 2023/0411513 A1, Dec. 21, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/266 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7813 (2013.01) [H01L 21/266 (2013.01); H01L 29/407 (2013.01); H01L 29/41741 (2013.01); H01L 29/66712 (2013.01); H01L 29/7804 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device manufacturing method, comprising:
forming a first semiconductor layer having a first conductive type at a main surface of a semiconductor substrate;
forming first opening portions at an interior of the first semiconductor layer;
forming an insulating film at bottom surface portions and side wall portions of the first opening portions, and forming concave portions;
forming first electrodes having the first conductive type at bottom surface portions of the concave portions;
forming second electrodes having a second conductive type at upper portions of the first electrodes, the second conductive type is a conductive type different from the first conductive type;
forming third electrodes at an interior of the insulating film;
forming a second semiconductor layer having the second conductive type at the first semiconductor layer at peripheries of the first opening portions; and
forming an impurity region having the first conductive type at an upper portion of the second semiconductor layer.