US 12,074,210 B2
Semiconductor device and method for manufacturing the same
Shunpei Yamazaki, Setagaya (JP); Hidekazu Miyairi, Isehara (JP); Kengo Akimoto, Atsugi (JP); and Kojiro Shiraishi, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 4, 2020, as Appl. No. 17/111,838.
Application 14/820,008 is a division of application No. 13/346,963, filed on Jan. 10, 2012, granted, now 9,111,804, issued on Aug. 18, 2015.
Application 13/346,963 is a division of application No. 13/013,054, filed on Jan. 25, 2011, granted, now 8,729,544, issued on May 20, 2014.
Application 17/111,838 is a continuation of application No. 15/656,173, filed on Jul. 21, 2017, granted, now 10,937,897.
Application 15/656,173 is a continuation of application No. 14/820,008, filed on Aug. 6, 2015, abandoned.
Application 13/013,054 is a continuation of application No. 12/511,285, filed on Jul. 29, 2009, granted, now 8,129,717, issued on Mar. 6, 2012.
Claims priority of application No. 2008-197145 (JP), filed on Jul. 31, 2008.
Prior Publication US 2021/0091210 A1, Mar. 25, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 21/46 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66969 (2013.01) [H01L 21/46 (2013.01); H01L 27/1225 (2013.01); H01L 29/7869 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a thin film transistor comprising:
a metal gate electrode over a glass substrate;
a gate insulating layer over the metal gate electrode;
an oxide semiconductor layer over the gate insulating layer;
a first metal layer over the oxide semiconductor layer;
a second metal layer over and in contact with the first metal layer;
a third metal layer over the oxide semiconductor layer; and
a fourth metal layer over and in contact with the third metal layer;
an insulating layer over the oxide semiconductor layer, the second metal layer, and the fourth metal layer, the insulating layer being in contact with a top surface of the oxide semiconductor layer; and
a pixel electrode over the insulating layer,
wherein a first gap between the first metal layer and the third metal layer is smaller than a second gap between the second metal layer and the fourth metal layer,
wherein the first gap is a distance between an upper end portion of the first metal layer and an upper end portion of the third metal layer, and the second gap is a distance between a lower end portion of the second metal layer and a lower end portion of the fourth metal layer,
wherein each of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer overlaps with the oxide semiconductor layer,
wherein each of the first metal layer and the second metal layer extends beyond an edge of the oxide semiconductor layer, and
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.