US 12,074,207 B2
Gate structure and method
Chung-Liang Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 23, 2023, as Appl. No. 18/340,758.
Application 18/340,758 is a continuation of application No. 17/190,888, filed on Mar. 3, 2021, granted, now 11,699,735.
Claims priority of provisional application 63/035,408, filed on Jun. 5, 2020.
Prior Publication US 2023/0343847 A1, Oct. 26, 2023
Int. Cl. H01L 29/49 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/4908 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/42364 (2013.01); H01L 29/42392 (2013.01); H01L 29/511 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a semiconductor nanostructure over a substrate; and
a gate structure over and laterally surrounding the semiconductor nanostructure, the gate structure including:
a first dielectric layer including a first dielectric material having dopants, wherein a greatest concentration of the dopants decreases as a distance to the semiconductor nanostructure decreases;
a second dielectric layer on the first dielectric layer, and including a second dielectric material substantially free of the dopants; and
a metal layer over the second dielectric layer.