US 12,074,206 B2
Integrated circuit device with improved reliability
Chia-Wei Chen, Hsinchu (TW); Chih-Yu Hsu, Hsinchu (TW); Hui-Chi Chen, Hsinchu County (TW); Shan-Mei Liao, Hsinchu (TW); Jian-Hao Chen, Hsinchu (TW); Cheng-Hao Hou, Hsinchu (TW); Huang-Chin Chen, Hsinchu (TW); Cheng Hong Yang, Hsinchu (TW); Shih-Hao Lin, Hsinchu (TW); Tsung-Da Lin, Hsinchu (TW); Da-Yuan Lee, Hsinchu (TW); Kuo-Feng Yu, Hsinchu County (TW); Feng-Cheng Yang, Hsinchu County (TW); Chi On Chui, Hsinchu (TW); and Yen-Ming Chen, Hsin-Chu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/461,499.
Prior Publication US 2023/0063857 A1, Mar. 2, 2023
Int. Cl. H01L 29/423 (2006.01); H01L 21/3105 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/3105 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 29/517 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a semiconductor substrate;
a fin structure on the semiconductor substrate;
a gate structure on the fin structure, the gate structure including:
an interfacial layer on the fin structure;
a gate dielectric layer on the interfacial layer, the gate dielectric layer including nitrogen element;
a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer; and
a pair of source/drain features on both sides of the gate structure,
wherein the gate dielectric layer comprises a first interface with the interfacial layer and a second interface with the gate electrode layer,
wherein a nitrogen concentration at the first interface is greater than a nitrogen concentration at the second interface.