CPC H01L 29/41733 (2013.01) [H01L 21/823475 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/775 (2013.01); H01L 29/78606 (2013.01); H01L 29/0653 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A method for forming a semiconductor structure, comprising:
sequentially stacking a first SiGe layer and a first Si layer over a substrate;
alternatingly stacked second SiGe layers and second Si layers over first Si layer, wherein a germanium concentration of the first SiGe layer is lower than a germanium concentration of the second SiGe layers;
patterning the second Si layers, the second SiGe layers, the first Si layer, the first SiGe layer and the substrate to form a fin structure;
forming a first source/drain recess in the fin structure;
forming a sacrificial contact in the first source/drain recess;
forming an etching stop layer on the sacrificial contact in the first source/drain recess;
forming a first source/drain feature on the etching stop layer in the first source/drain recess;
removing the second SiGe layers and the first Si layer to form gaps; and
forming a gate stack to fill the gaps.
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