US 12,074,194 B2
Semiconductor device
Kanako Komatsu, Yokohama Kanagawa (JP); and Daisuke Shinohara, Yokohama Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Mar. 3, 2022, as Appl. No. 17/686,014.
Claims priority of application No. 2021-154191 (JP), filed on Sep. 22, 2021.
Prior Publication US 2023/0087733 A1, Mar. 23, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0607 (2013.01) [H01L 29/41775 (2013.01); H01L 29/42356 (2013.01); H01L 29/7816 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate;
a first well of a first conductivity type in a surface region that comprises a surface of the semiconductor substrate;
a first impurity region of a second conductivity type in a region of a surface of the first well;
a second impurity region of the first conductivity type, a portion of the first well being located between the second impurity region and the first impurity region in the surface region of the semiconductor substrate;
a first insulating body on the surface of the semiconductor substrate;
a gate electrode extending over part of the first well and part of the second impurity region on the first insulating body;
an interconnection extending in a region above the gate electrode and the first insulating body;
a second insulating body extending on an upper surface of the gate electrode and over a region above the second impurity region; and
a first conductive body on the second insulating body and below the interconnection.