US 12,074,183 B2
Semiconductor packaging method and semiconductor package device
Guoqing Yu, Nantong (CN)
Assigned to TONGFU MICROELECTRONICS CO., LTD., Nantong (CN)
Filed by TONGFU MICROELECTRONICS CO., LTD., Nantong (CN)
Filed on May 5, 2021, as Appl. No. 17/308,648.
Application 17/308,648 is a continuation of application No. PCT/CN2019/082308, filed on Apr. 11, 2019.
Claims priority of application No. 201811341281.1 (CN), filed on Nov. 12, 2018; application No. 201811341297.2 (CN), filed on Nov. 12, 2018; and application No. 201811341984.4 (CN), filed on Nov. 12, 2018.
Prior Publication US 2021/0343763 A1, Nov. 4, 2021
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/1462 (2013.01) [H01L 27/14618 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 27/14685 (2013.01); H01L 27/14687 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor packaging method, comprising:
providing a chip, wherein the chip includes:
a chip substrate having a front surface and a back surface, wherein the front surface includes a photosensitive region;
soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region;
a metal part formed on a side of each soldering pad facing away from the chip substrate; and
a transparent protective layer formed on the front surface of the chip substrate, wherein the transparent protective layer covers the photosensitive region of the chip substrate the transparent protective layer encapsulates an entire sidewall of the metal part, and the transparent protective layer contains an opening at a position corresponding to the metal part to expose a first end of the metal part away from the soldering pads; and
electrically connecting the first end of the metal part to a circuit board using a conductive connection part to electrically connect the chip with the circuit board, the conductive connection part including:
a first portion electrically connecting to the first end of the metal part, the sidewall of the chip substrate being coplanar with the sidewall of the transparent protective layer, and
a second portion in parallel with the coplanar sidewalls of the chip substrate and the transparent protective layer.