US 12,074,170 B2
Display device and tiled display device including the same
Cheol Min Park, Hwaseong-si (KR); Yi Joon Ahn, Seoul (KR); Atsushi Nemoto, Suwon-si (KR); Woo Suk Seo, Yongin-si (KR); Eun Kyung Yeon, Suwon-si (KR); Jae Been Lee, Seoul (KR); and Tae Ho Lee, Hwaseong-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Oct. 15, 2021, as Appl. No. 17/451,028.
Claims priority of application No. 10-2020-0166239 (KR), filed on Dec. 2, 2020.
Prior Publication US 2022/0173126 A1, Jun. 2, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 25/16 (2023.01)
CPC H01L 27/1218 (2013.01) [H01L 25/162 (2013.01); H01L 25/167 (2013.01); H01L 27/124 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A tiled display device comprising:
a plurality of display devices comprising a plurality of display areas comprising a plurality of pixels, and a coupling area between adjacent display areas from among the plurality of display areas,
wherein each of the plurality of display devices comprises:
a substrate comprising a first portion configured to support the display area, a second portion extending from the first portion to be bent, and a third portion extending from the second portion;
a thin film transistor layer on the first portion, the second portion, and the third portion of the substrate and comprising a thin film transistor;
a display layer comprising the thin film transistor on the first portion of the substrate, and the plurality of pixels;
a connection line at an edge of the first portion of the substrate and connected to the plurality of pixels;
a pad portion on the third portion of the substrate;
a fan-out line on the second portion of the substrate and connected between the pad portion and the connection line; and
a plurality of pattern holes penetrating the thin film transistor layer and the second portion of the substrate.