US 12,074,168 B2
Semiconductor device and method of manufacturing the same
Guo-Huei Wu, Tainan (TW); Jerry Chang Jui Kao, Taipei (TW); Chih-Liang Chen, Hsinchu (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Jung-Chan Yang, Taoyuan County (TW); Lee-Chung Lu, Taipei (TW); and Xiangdong Chen, San Diego, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Hsinchu (TW)
Filed on Apr. 18, 2023, as Appl. No. 18/136,216.
Application 18/136,216 is a continuation of application No. 17/373,548, filed on Jul. 12, 2021, granted, now 11,664,380.
Application 17/373,548 is a continuation of application No. 16/797,890, filed on Feb. 21, 2020, granted, now 11,063,045, issued on Jul. 13, 2021.
Claims priority of provisional application 62/834,117, filed on Apr. 15, 2019.
Prior Publication US 2023/0253406 A1, Aug. 10, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 23/528 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 23/5286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device having a standard cell, the standard cell comprising:
a first gate-all-around field effect transistor (GAA FET) disposed over a substrate;
a second GAA FET disposed at a vertically different level from the first GAA FET and sharing a gate with the first GAA FET;
a first power supply line;
a second power supply line; and
a first signal line, a second signal line, a third signal line and a fourth signal line, which are disposed above the first GAA FET and the second GAA FET, wherein:
the first, second, third and fourth signal lines are located at a same level with each other,
the first power supply line and the second power supply line are located at vertically different levels from each other, and
a cell height of the standard cell is 4 T, where T is a pitch between the first and second signal lines, the second and third signal lines, and the third and fourth signal lines in plan view.