US 12,074,167 B2
Hybrid scheme for improved performance for P-type and N-type FinFETs
Kuo-Cheng Chiang, Zhubei (TW); Shi Ning Ju, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); Kuan-Lun Cheng, Hsinchu (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 7, 2022, as Appl. No. 18/053,236.
Application 16/205,443 is a division of application No. 15/691,852, filed on Aug. 31, 2017, granted, now 10,269,803, issued on Apr. 23, 2019.
Application 18/053,236 is a continuation of application No. 17/120,637, filed on Dec. 14, 2020, granted, now 11,495,598.
Application 17/120,637 is a continuation of application No. 16/900,264, filed on Jun. 12, 2020, granted, now 10,868,015, issued on Dec. 15, 2020.
Application 16/900,264 is a continuation of application No. 16/740,911, filed on Jan. 13, 2020, granted, now 10,868,014, issued on Dec. 15, 2020.
Application 16/740,911 is a continuation of application No. 16/205,443, filed on Nov. 30, 2018, granted, now 10,535,656, issued on Jan. 14, 2020.
Prior Publication US 2023/0113266 A1, Apr. 13, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/30604 (2013.01); H01L 21/3081 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/76229 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 27/0922 (2013.01); H01L 27/1207 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 21/30625 (2013.01); H01L 21/823807 (2013.01); H01L 21/823828 (2013.01); H01L 29/045 (2013.01); H01L 29/165 (2013.01); H01L 29/7848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
etching a semiconductor substrate to form:
a first semiconductor strip in a first device region, wherein the first semiconductor strip has a first top surface crystal orientation; and
a second semiconductor strip in a second device region; and
forming an isolation region comprising:
a bulk portion comprising a first sidewall contacting the first semiconductor strip, and a second sidewall contacting the second semiconductor strip; and
a protruding portion protruding from a bottom surface of the bulk portion downwardly to a level lower than bottoms of the first semiconductor strip and the second semiconductor strip, wherein the protruding portion recesses laterally from the first sidewall and the second sidewall toward a first middle line between the first sidewall and the second sidewall; and
forming a source/drain region overlapping the first semiconductor strip, wherein the source/drain region comprises:
a lower portion having the first top surface crystal orientation; and
an upper portion over the lower portion, wherein the upper portion has a second top surface crystal orientation different from the first top surface crystal orientation.