US 12,074,164 B2
FinFET pitch scaling
Kuan-Ting Pan, Taipei (TW); Yi-Ruei Jhan, Keelung (TW); Kuo-Cheng Chiang, Hsinchu County (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/815,185.
Application 17/815,185 is a division of application No. 16/888,457, filed on May 29, 2020, granted, now 11,527,533.
Prior Publication US 2022/0367455 A1, Nov. 17, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first set of fin structures on a substrate;
forming a sacrificial material between fin structures within the first set of fin structures;
forming a dummy gate with a planar bottom surface over the fin structures and the sacrificial material;
forming sidewall structures on the dummy gate;
laterally etching the sacrificial material underneath the sidewall structures;
depositing a lower sidewall structure where the sacrificial material was removed.