US 12,074,160 B2
Isolated 3D semiconductor device package with transistors attached to opposing sides of leadframe sharing leads
Tiburcio A. Maldo, Consolacion (PH); Keunhyuk Lee, Suzhou (CN); and Jerome Teysseyre, Scottsdale, AZ (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Oct. 1, 2020, as Appl. No. 16/948,796.
Claims priority of provisional application 62/705,840, filed on Jul. 17, 2020.
Prior Publication US 2022/0020740 A1, Jan. 20, 2022
Int. Cl. H01L 27/06 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01)
CPC H01L 27/0664 (2013.01) [H01L 21/4825 (2013.01); H01L 21/4839 (2013.01); H01L 23/13 (2013.01); H01L 23/49861 (2013.01); H01L 27/0629 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device package, comprising:
a first transistor attached to a first substrate and to a first surface of a leadframe, with first transistor power leads on a side of the leadframe; and
a second transistor attached to a second substrate and to a second surface of the leadframe, with second transistor power leads in planar contact with corresponding leads of the leadframe on the side of the leadframe.