US 12,074,156 B2
Memory array circuit and method of manufacturing same
Hidehiro Fujiwara, Hsinchu (TW); Sahil Preet Singh, Hsinchu (TW); Chih-Yu Lin, Hsinchu (TW); Hsien-Yu Pan, Hsinchu (TW); Yen-Huei Chen, Hsinchu (TW); and Hung-Jen Liao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 25, 2021, as Appl. No. 17/213,074.
Application 17/213,074 is a division of application No. 15/904,959, filed on Feb. 26, 2018, granted, now 10,964,683.
Claims priority of provisional application 62/552,358, filed on Aug. 30, 2017.
Prior Publication US 2021/0217742 A1, Jul. 15, 2021
Int. Cl. H01L 27/02 (2006.01); G11C 5/06 (2006.01); G11C 7/18 (2006.01); H01L 23/522 (2006.01); H10B 10/00 (2023.01)
CPC H01L 27/0207 (2013.01) [G11C 5/063 (2013.01); G11C 7/18 (2013.01); H01L 23/5226 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory array comprising:
a first memory cell configured to store first data, the first memory cell being in a first column of memory cells arranged in a first direction;
a second memory cell configured to store second data, the second memory cell being in the first column of memory cells, and being separated from the first memory cell in the first direction;
a first set of memory cells configured to store third data, the first set of memory cells being in the first column of memory cells, and being between the first memory cell and the second memory cell; and
a bit line bar extending along the first direction, and being over the first memory cell, the second memory cell and the first set of memory cells, the bit line bar comprising:
a first conductor extending in the first direction, and being in a first conductive layer; and
a second conductor extending in the first direction, and being in a second conductive layer different from the first conductive layer.