US 12,074,134 B2
Package for stress sensitive component and semiconductor device
Anindya Poddar, Sunnyvale, CA (US); Mahmud Chowdhury, Richardson, TX (US); Hau Nguyen, San Jose, CA (US); Masamitsu Matsuura, Beppu (JP); and Ting-Ta Yen, San Jose, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jun. 30, 2021, as Appl. No. 17/364,769.
Prior Publication US 2023/0005881 A1, Jan. 5, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/94 (2013.01) [H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 23/3171 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 24/95 (2013.01); H01L 2224/10126 (2013.01); H01L 2224/10145 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/16146 (2013.01); H01L 2225/06513 (2013.01); H01L 2924/182 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first semiconductor die with a component on a first surface, the first semiconductor die having an opposite second surface;
a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate;
a solder seal bonded to and extending from the first surface of the first semiconductor die which is flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the component;
a first solder joint formed between the solder seal and a dielectric material overlying the third surface of the second semiconductor die, the first solder joint physically contacting the dielectric material;
a post connect extending from the first surface of the first semiconductor die;
a second solder joint formed between solder at an end of the post connect and a conductive land on a dielectric layer overlying the third surface of the second semiconductor die; and
a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.