US 12,074,122 B2
Inductor structure, semiconductor package and fabrication method thereof
Chih-Yuan Chang, Hsinchu (TW); Jiun-Yi Wu, Taoyuan (TW); Chien-Hsun Lee, Hsin-chu County (TW); Chung-Shi Liu, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 16, 2023, as Appl. No. 18/301,246.
Application 18/301,246 is a continuation of application No. 17/218,059, filed on Mar. 30, 2021, granted, now 11,658,134.
Prior Publication US 2023/0253348 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 49/02 (2006.01); H03H 7/01 (2006.01)
CPC H01L 23/645 (2013.01) [H01L 21/4857 (2013.01); H01L 23/145 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 28/10 (2013.01); H01L 28/40 (2013.01); H03H 7/0115 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19103 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A structure, comprising:
a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer;
a first metal pattern disposed on the first via and embedded in a second dielectric layer;
a first conductive via disposed on the first conductive line and embedded in the second dielectric layer, wherein the first metal pattern and the first conductive via are spaced apart from each other by the second dielectric layer, and the first metal pattern has a ring shape with two opposite terminals not joined;
a second via disposed on the first metal pattern and embedded in a third dielectric layer;
a second conductive line disposed on the second conductive via and embedded in the third dielectric layer;
a second metal pattern disposed on the second via and embedded in a fourth dielectric layer; and
a second conductive via disposed on the second conductive line and embedded in the fourth dielectric layer, wherein the second metal pattern and the second conductive via are spaced apart from each other by the fourth dielectric layer, the second metal pattern has a ring shape with two opposite terminals not joined, and the two opposite terminals of the first metal pattern do not vertically overlap the two opposite terminals of the second metal pattern,
wherein the first via, the first metal pattern, the second via and the second metal pattern are electrically connected, and an inductor structure including the first via, the first metal pattern, the second via and the second metal pattern extends from the first dielectric layer to the fourth dielectric layer.