US 12,074,121 B2
Metal-free frame design for silicon bridges for semiconductor packages
Dae-Woo Kim, Phoenix, AZ (US); Sujit Sharan, Chandler, AZ (US); and Sairam Agraharam, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 30, 2023, as Appl. No. 18/128,954.
Application 18/128,954 is a continuation of application No. 18/114,123, filed on Feb. 24, 2023.
Application 18/114,123 is a continuation of application No. 17/143,142, filed on Jan. 6, 2021, granted, now 11,626,372.
Application 17/143,142 is a continuation of application No. 16/576,520, filed on Sep. 19, 2019, granted, now 10,916,514, issued on Feb. 9, 2021.
Application 16/576,520 is a continuation of application No. 15/749,744, granted, now 10,461,047, issued on Oct. 29, 2019, previously published as PCT/US2015/058074, filed on Oct. 29, 2015.
Prior Publication US 2023/0238339 A1, Jul. 27, 2023
Int. Cl. H01L 23/538 (2006.01); G01R 31/27 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/544 (2006.01); H01L 23/58 (2006.01); H01L 23/14 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01)
CPC H01L 23/585 (2013.01) [G01R 31/275 (2013.01); H01L 22/32 (2013.01); H01L 23/49827 (2013.01); H01L 23/522 (2013.01); H01L 23/5385 (2013.01); H01L 23/544 (2013.01); H01L 24/14 (2013.01); H01L 23/147 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/14 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/171 (2013.01); H01L 2224/17153 (2013.01); H01L 2224/17177 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/81132 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/3512 (2013.01); H10B 80/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate having an insulating layer thereon, the substrate comprising silicon;
a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;
a first metal ring in the dielectric material stack and continuous around the conductive routing, wherein the first metal ring comprises a vertical stack of alternating metal lines and vias, the alternating metal lines comprising a first metal line, a second metal line above the first metal line, a third metal line above the second metal line, and a fourth metal line above the third metal line;
a second metal ring in the dielectric material stack and continuous around the first metal ring; and
a plurality of staggered non-continuous metal rings adjacent to the second metal ring.