US 12,074,119 B2
Chip package structure
Jiun-Ting Chen, Hsinchu (TW); Ying-Ching Shih, Hsinchu (TW); Szu-Wei Lu, Hsinchu (TW); and Chih-Wei Wu, Zhuangwei Township, Yilan County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 18, 2023, as Appl. No. 18/319,610.
Application 17/392,868 is a division of application No. 16/395,385, filed on Apr. 26, 2019, granted, now 11,088,086, issued on Aug. 10, 2021.
Application 18/319,610 is a continuation of application No. 17/392,868, filed on Aug. 3, 2021, granted, now 11,694,975.
Prior Publication US 2023/0307381 A1, Sep. 28, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 21/563 (2013.01); H01L 23/3157 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package structure, comprising:
a substrate;
a first chip structure and a second chip structure over the substrate;
an anti-warpage bar between the first chip structure and the second chip structure, wherein the anti-warpage bar is separated from the first chip structure and the second chip structure by an adhesive layer; and
an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate, wherein a topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar, wherein the underfill layer is in direct contact with a bottom surface of the adhesive layer.