US 12,074,111 B2
Semiconductor devices including metal gate protection and methods of fabrication thereof
Sheng-Tsung Wang, Hsinchu (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 26, 2023, as Appl. No. 18/139,578.
Application 18/139,578 is a continuation of application No. 17/185,817, filed on Feb. 25, 2021, granted, now 11,640,941.
Prior Publication US 2023/0268277 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/535 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a gate dielectric layer;
a gate electrode layer in contact with the gate dielectric layer;
a self-aligned contact (SAC) layer disposed over the gate electrode layer;
an isolation layer disposed over the gate electrode layer;
a first sidewall spacer in contact with the gate dielectric layer; and
a liner layer having a first portion disposed between the isolation layer and the gate electrode layer and a second portion disposed between and in contact with the first sidewall spacer and the SAC layer.