CPC H01L 23/5228 (2013.01) [H01L 21/762 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 28/20 (2013.01)] | 20 Claims |
1. A semiconductor device, comprising:
a first metal line;
a first punch stop layer having a first top surface that is substantially level with a second top surface of the first metal line;
a resistive element disposed over the first punch stop layer;
a first conductive via in contact with both the first top surface of the first punch stop layer and first sidewall surfaces of the resistive element; and
a third conductive via in contact with the second top surface of the first metal line, wherein a first top edge of the first conductive via is offset from a second top edge of the third conductive via.
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