US 12,074,104 B2
Integrated circuit packages with ring-shaped substrates
Po-Hao Tsai, Zhongli (TW); Techi Wong, Zhubei (TW); Meng-Wei Chou, Zhubei (TW); Meng-Liang Lin, Hsinchu (TW); Po-Yao Chuang, Hsinchu (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 12, 2022, as Appl. No. 18/064,417.
Application 17/034,805 is a division of application No. 16/207,850, filed on Dec. 3, 2018, granted, now 10,790,162, issued on Sep. 29, 2020.
Application 18/064,417 is a continuation of application No. 17/034,805, filed on Sep. 28, 2020, granted, now 11,527,474.
Claims priority of provisional application 62/737,246, filed on Sep. 27, 2018.
Prior Publication US 2023/0105359 A1, Apr. 6, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/56 (2013.01); H01L 21/563 (2013.01); H01L 21/76871 (2013.01); H01L 21/76877 (2013.01); H01L 23/3121 (2013.01); H01L 23/49827 (2013.01); H01L 24/09 (2013.01); H01L 24/14 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
an integrated circuit die;
a ring-shaped substrate surrounding the integrated circuit die, the ring-shaped substrate comprising a core and conductive vias extending through the core;
an encapsulant surrounding the ring-shaped substrate and the integrated circuit die, the encapsulant extending through the ring-shaped substrate, the encapsulant extending along outer sidewalls of the ring-shaped substrate; and
a first redistribution structure on the encapsulant, the first redistribution structure comprising first redistribution lines connected to the conductive vias of the ring-shaped substrate, the first redistribution structure further comprising a dielectric layer contacting the encapsulant, a top surface of the dielectric layer having a higher degree of planarity than a bottom surface of the dielectric layer.