US 12,074,101 B2
Package structure and method of fabricating the same
Yu-Sheng Lin, Hsinchu County (TW); Han-Hsiang Huang, Hsinchu (TW); Chien-Sheng Chen, Hsinchu (TW); Shu-Shen Yeh, Taoyuan (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 22, 2023, as Appl. No. 18/472,271.
Application 18/472,271 is a continuation of application No. 17/376,186, filed on Jul. 15, 2021, granted, now 11,823,887.
Claims priority of provisional application 63/163,055, filed on Mar. 19, 2021.
Prior Publication US 2024/0014120 A1, Jan. 11, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49838 (2013.01) [H01L 21/4853 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49811 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2221/68331 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure, comprising:
a substrate;
a semiconductor package disposed on the substrate;
first bump structures and second bump structures disposed in between the substrate and the semiconductor package, and electrically connecting the substrate to the semiconductor package, wherein the second bump structures are located on at least two sides of the first bump structures, and the first bump structures and the second bump structures have different heights, and
wherein a warpage of the semiconductor package is equal to or greater than 45 μm, and the maximum width W1 of the first bump structures and the maximum width W2 of the second bump structures fulfills the following relationship: W1>W2≥0.90*W1.