US 12,074,099 B2
Microelectronics package assemblies and processes for making
Ramesh Kothandapani, Singapore (SG); Christopher Johnson, Mayfield Heights, OH (US); ZhenWei Tee, Mayfield Heights, OH (US); Noel De Leon, Mayfield Heights, OH (US); and SinLi Tan, Singapore (SG)
Assigned to Materion Corporation, Mayfield Heights, OH (US)
Filed by Materion Corporation, Mayfield Heights, OH (US)
Filed on May 5, 2022, as Appl. No. 17/737,564.
Claims priority of provisional application 63/185,768, filed on May 7, 2021.
Prior Publication US 2022/0359351 A1, Nov. 10, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/373 (2006.01); H01L 23/66 (2006.01)
CPC H01L 23/49568 (2013.01) [H01L 21/4828 (2013.01); H01L 21/4842 (2013.01); H01L 23/3732 (2013.01); H01L 23/49558 (2013.01); H01L 23/49562 (2013.01); H01L 23/49582 (2013.01); H01L 23/49586 (2013.01); H01L 23/66 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronics package assembly comprising:
a flange having an upper surface, wherein the flange is a high thermal conductive material having a thermal conductivity ranging from 140 to 2000 W/(mK) at room temperature and a coefficient of thermal expansion (CTE) ranging from 2.3 ppm/K to 17.5 ppm/K;
a first coating disposed on the upper surface of the flange;
an insulator for partially enclosing a die, the insulator having a bottom surface for mounting onto the flange and an upper surface opposite the bottom surface,
a second coating disposed on the bottom surface of the insulator and a third coating disposed on the upper surface of the insulator,
wherein the first coating, the second coating, and the third coating each have a thickness of less than or equal to 1 micron, and wherein at least one of the first coating, the second coating, and the third coating is applied via at least one of physical vapor deposition, atomic deposition, or chemical deposition.