US 12,074,092 B2
Hard IP blocks with physically bidirectional passageways
Javier A. Delacruz, San Jose, CA (US)
Assigned to Adeia Semiconductor Inc., San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR INC., San Jose, CA (US)
Filed on Feb. 10, 2021, as Appl. No. 17/172,756.
Application 17/172,756 is a continuation of application No. 16/426,515, filed on May 30, 2019, granted, now 10,923,413, issued on Feb. 16, 2021.
Claims priority of provisional application 62/678,206, filed on May 30, 2018.
Prior Publication US 2021/0166995 A1, Jun. 3, 2021
Int. Cl. H01L 23/48 (2006.01); G06F 13/40 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/481 (2013.01) [G06F 13/4027 (2013.01); H01L 23/528 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of fabricating a hard IP block, comprising:
defining one or more keepout zones for the hard IP block comprising a serializer/deserializer (SerDes);
forming a base for the hard IP block, the base having a top surface and a bottom surface;
forming a circuitry layer on the top surface of the base, the circuitry layer comprising circuitry for the SerDes in areas around the one or more keepout zones such that each of the keepout zones is exclusive of the circuitry;
forming through-hole interconnects through the keepout zones; and
hybrid direct bonding the hard IP block to a host substrate such that a surface of the hard IP block contacts a top surface of the host substrate without an intervening material therebetween.