US 12,074,069 B2
Semiconductor device and integrated circuit in hybrid row height structure
Jerry Chang-Jui Kao, Taipei (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Li-Chung Hsu, Hsinchu (TW); Sung-Yen Yeh, Pingtung County (TW); Yung-Chen Chien, Kaohsiung (TW); Jung-Chan Yang, Taoyuan (TW); and Tzu-Ying Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jun. 2, 2022, as Appl. No. 17/831,108.
Application 17/831,108 is a continuation of application No. 16/882,103, filed on May 22, 2020, granted, now 11,355,395.
Prior Publication US 2022/0293469 A1, Sep. 15, 2022
Int. Cl. H01L 23/535 (2006.01); H01L 21/48 (2006.01); H01L 21/822 (2006.01); H01L 23/50 (2006.01)
CPC H01L 21/8221 (2013.01) [H01L 21/4828 (2013.01); H01L 23/50 (2013.01); H01L 23/535 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of first cell rows extending in a first direction, each of the first cell rows having a first row height, wherein a first row of the plurality of first cell rows is configured for a first cell to be arranged, wherein the first cell comprises a first two-fins active area of a first conductivity type and a second two-fins active area of a second conductivity type different from the first conductivity type;
a plurality of second cell rows extending in the first direction, each of the second cell rows having a second row height that is different from the first row height;
wherein at least one row of the plurality of second cell rows includes a portion for at least one second cell to be arranged, wherein the portion has a third row height that is different from each of the first row height and the second row height, wherein the at least one second cell comprises at least one one-fin active area of the second conductivity type, and the second two-fins active area is separated from the at least one one-fin active area and interposed between the first two-fins active area and the at least one one-fin active area; and
a gate extending through the first row of the plurality of first cell rows and the at least one row of the plurality of second cell rows to cross the first to second two-fins active areas and the at least one one-fin active area,
wherein the gate is shared by two transistors that are coupled in parallel with each other.