US 12,074,068 B2
Epitaxial structures for stacked semiconductor devices
Mrunal Abhijith Khaderbad, Hsinchu (TW); Sathaiya Mahaveer Dhanyakumar, Hsinchu (TW); Huicheng Chang, Tainan (TW); Keng-Chu Lin, Ping-Tung (TW); and Winnie Victoria Wei-Ning Chen, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/461,271.
Prior Publication US 2023/0068065 A1, Mar. 2, 2023
Int. Cl. H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01)
CPC H01L 21/8221 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823481 (2013.01); H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor device of a first type, comprising:
a first plurality of nanostructures;
a first pair of source/drain structures; and
a first gate electrode on the first plurality of nanostructures;
a second transistor device of a second type formed over the first transistor device, the second transistor device comprising:
a second plurality of nanostructures over the first plurality of nanostructures;
a second pair of source/drain structures over the first pair of source/drain structures; and
a second gate electrode on the second plurality of nanostructures and over the first plurality of nanostructures;
a first isolation structure between the first and second pluralities of nanostructures;
a second isolation structure in contact with a top surface of the first pair of source/drain structures; and
a seed layer between the second isolation structure and the second pair of source/drain structures.