US 12,074,066 B2
Integrated circuit component with conductive terminals of different dimensions and package structure having the same
Ming-Yen Chiu, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 22, 2022, as Appl. No. 17/846,021.
Application 17/846,021 is a continuation of application No. 15/706,781, filed on Sep. 18, 2017, granted, now 11,417,569.
Prior Publication US 2022/0319925 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/78 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/544 (2006.01); H01L 23/58 (2006.01)
CPC H01L 21/78 (2013.01) [H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/544 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 24/15 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/5448 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16265 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/214 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/94 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
an integrated circuit component, comprising:
a semiconductor die;
conductive vias, disposed on and electrically coupled to the semiconductor die, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the semiconductor die;
alignment marks, disposed on and electrically isolated from the semiconductor die, wherein a thickness of each of the alignment marks is less than a thickness of each of the conductive vias along a stacking direction of the conductive vias and the semiconductor die; and
a protection layer, covering the semiconductor die and at least in contact with sidewalls of the conductive vias and sidewalls of the alignment marks, wherein top surfaces of the alignment marks, top surfaces of the first group of the conductive vias and top surfaces of the second group of the conductive vias are substantially coplanar to a top surface of the protection layer; and
a first redistribution circuit structure, disposed on and electrically connected to the integrated circuit component, wherein the first redistribution circuit structure is electrically connected to the conductive vias and is electrically isolated from the alignment marks.