US 12,074,061 B2
Field effect transistor with multi-metal gate via and method
Sheng-Tsung Wang, Hsinchu (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, Hsinchu (TW); Sung-Li Wang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 19, 2021, as Appl. No. 17/407,083.
Prior Publication US 2023/0053595 A1, Feb. 23, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/76846 (2013.01) [H01L 23/5226 (2013.01); H01L 29/401 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a substrate;
a gate structure wrapping around a vertical stack of nanostructure semiconductor channels;
a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels; and
a gate via in contact with the gate structure, including:
a metal liner layer having a first flowability; and
a metal fill layer having a second flowability higher than the first flowability of the metal liner layer.