CPC H01L 21/76846 (2013.01) [H01L 23/5226 (2013.01); H01L 29/401 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A device, comprising:
a substrate;
a gate structure wrapping around a vertical stack of nanostructure semiconductor channels;
a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels; and
a gate via in contact with the gate structure, including:
a metal liner layer having a first flowability; and
a metal fill layer having a second flowability higher than the first flowability of the metal liner layer.
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