US 12,074,060 B2
Semiconductor device structure and methods of forming the same
Cheng-Chin Lee, Taipei (TW); Shao-Kuan Lee, Kaohsiung (TW); Kuang-Wei Yang, Hsinchu (TW); Cherng-Shiaw Tsai, New Taipei (TW); Hsin-Yen Huang, New Taipei (TW); Hsiaokang Chang, Hsinchu (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTORMANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 28, 2021, as Appl. No. 17/460,173.
Prior Publication US 2023/0067027 A1, Mar. 2, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76837 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a conductive layer over a layer;
forming one or more openings in the conductive layer to form one or more conductive features and to expose portions of the layer;
forming a liner on each of the one or more conductive features;
selectively forming a first dielectric material in the openings; and
selectively forming a first dielectric layer over each first dielectric material, wherein a top surface of the first dielectric layer is substantially co-planar with a top surface of the liner.