US 12,074,059 B2
Semiconductor arrangement and method of making
Hsi-Wen Tien, Xinfeng Township (TW); Wei-Hao Liao, Taichung (TW); Pin-Ren Dai, Taipei (TW); Chih Wei Lu, Hsinchu (TW); and Chung-Ju Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/225,736.
Application 18/225,736 is a continuation of application No. 17/536,345, filed on Nov. 29, 2021, granted, now 11,776,845.
Application 17/536,345 is a continuation of application No. 16/837,087, filed on Apr. 1, 2020, granted, now 11,189,524, issued on Nov. 30, 2021.
Prior Publication US 2023/0369099 A1, Nov. 16, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 21/76807 (2013.01) [H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 2221/1031 (2013.01)] 20 Claims
OG exemplary drawing
 
10. A semiconductor arrangement, comprising:
a metal layer overlying a substrate;
a conductive structure penetrating through the metal layer to the substrate and contacting the metal layer; and
a first dielectric layer surrounding at least four sides of the conductive structure and contacting the metal layer.