US 12,074,056 B2
Method for producing an advanced substrate for hybrid integration
Walter Schwarzenbach, Saint Nazaire les Eymes (FR)
Assigned to Soitec, Bernin (FR)
Filed by Soitec, Bernin (FR)
Filed on Oct. 17, 2022, as Appl. No. 18/047,113.
Application 18/047,113 is a division of application No. 17/276,107, granted, now 11,476,153, previously published as PCT/EP2019/074276, filed on Sep. 11, 2019.
Claims priority of application No. 1800972 (FR), filed on Sep. 14, 2018.
Prior Publication US 2023/0063362 A1, Mar. 2, 2023
Int. Cl. H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01)
CPC H01L 21/76254 (2013.01) [H01L 21/84 (2013.01); H01L 27/1207 (2013.01); H01L 21/02532 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A substrate, comprising:
a receiver substrate;
an active layer comprising single-crystal semiconductor material; and
an electrically insulating silicon oxide layer interposed between the active layer and the receiver substrate; and
a polycrystalline silicon layer on the receiver substrate, the polycrystalline silicon layer coated with the electrically insulating silicon oxide layer so as to define a first portion of the electrically insulating silicon oxide layer having a first thickness and interposed between the polycrystalline silicon layer and the active layer, and a second portion of the electrically insulating silicon oxide layer having a second thickness greater than the first thickness, the second portion being located between the receiver substrate and the active layer.