US 12,074,037 B2
Packaging method for circuit units comprising circuit baseplate
Haisheng Wang, Shandong (CN); Dewen Tian, Shandong (CN); and Qinglin Song, Shandong (CN)
Assigned to Weifang Goertek Microelectronics Co., Ltd., Shandong (CN)
Appl. No. 17/620,796
Filed by Weifang Goertek Microelectronics Co., Ltd., Shandong (CN)
PCT Filed Dec. 6, 2019, PCT No. PCT/CN2019/123558
§ 371(c)(1), (2) Date Dec. 20, 2021,
PCT Pub. No. WO2020/253148, PCT Pub. Date Dec. 24, 2020.
Claims priority of application No. 201910529562.8 (CN), filed on Jun. 18, 2019.
Prior Publication US 2022/0406619 A1, Dec. 22, 2022
Int. Cl. H01L 23/552 (2006.01); H01L 21/306 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/561 (2013.01) [H01L 21/30604 (2013.01); H01L 23/552 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A packaging method for circuit units, wherein the circuit units comprise a silicon layer substrate and a silicon dioxide layer overlaid on the silicon layer substrate, comprising:
attaching a plurality of circuit units to a circuit baseplate in a spaced apart and an inverted mode, wherein the silicon dioxide layer is attached to the circuit baseplate, and the silicon layer substrate faces away from the circuit baseplate;
forming an insulator between each of the plurality of circuit units;
removing the silicon layer substrate to expose the silicon dioxide layer; and
forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.