US 12,074,028 B2
Semiconductor device and manufacturing method thereof
Chandrashekhar Prakash Savant, Hsinchu (TW); Tien-Wei Yu, Kaohsiung (TW); and Chia-Ming Tsai, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Nov. 7, 2022, as Appl. No. 18/053,234.
Application 18/053,234 is a continuation of application No. 17/081,879, filed on Oct. 27, 2020, granted, now 11,495,463.
Prior Publication US 2023/0122103 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/28088 (2013.01) [H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 27/0924 (2013.01); H01L 29/4966 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a gate dielectric layer on a fin structure;
forming a work function layer on the gate dielectric layer;
forming a capping layer on the work function layer;
forming a barrier layer on the capping layer;
performing a hydrogen treatment on the work function layer, the capping layer, and the barrier layer after forming the barrier layer; and
forming a glue layer on the barrier layer after performing the hydrogen treatment.