US 12,073,918 B2
Memory device deserializer circuit with a reduced form factor
Guan Wang, San Jose, CA (US); and Luigi Pilolli, L'Aquila (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 17, 2023, as Appl. No. 18/097,668.
Application 18/097,668 is a division of application No. 17/340,754, filed on Jun. 7, 2021, granted, now 11,594,268.
Prior Publication US 2023/0162770 A1, May 25, 2023
Int. Cl. G11C 8/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); H03K 3/356 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/106 (2013.01); G11C 7/1087 (2013.01); H03K 3/356095 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory sub-system comprising:
a memory device comprising a circuit operatively coupled to an array data bus of a memory array; and
control logic, operatively coupled with the circuit, to perform operations comprising:
deserializing a serial data stream in a first time domain to generate at least one of a set of rising data portions or a set of falling data portions; and
synchronizing the at least one of the set of rising data portions or the set of falling data portions in a second time domain using at least one of a set of rising edge clock signals or a set of falling edge clock signals generated by a ring counter portion.