US 12,073,917 B2
Memory device that includes a duty correction circuit, memory controller that includes a duty sensing circuit, and storage device that includes a memory device
Tongsung Kim, Suwon-si (KR); Youngmin Jo, Hwaseong-si (KR); Manjae Yang, Hwaseong-si (KR); Chiweon Yoon, Seoul (KR); Junha Lee, Seoul (KR); and Byunghoon Jeong, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 17, 2021, as Appl. No. 17/404,510.
Claims priority of application No. 10-2021-0008911 (KR), filed on Jan. 21, 2021.
Prior Publication US 2022/0230666 A1, Jul. 21, 2022
Int. Cl. G06F 1/04 (2006.01); G06F 3/06 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01); G11C 5/14 (2006.01)
CPC G11C 7/222 (2013.01) [G06F 1/04 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 5/145 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A storage device comprising:
a duty sensing chip configured to generate a clock signal, the duty sensing chip comprising a plurality of duty sensing circuits, each duty sensing circuit of the plurality of duty sensing circuits respectively configured to generate a positive signal and a negative signal based on a data signal of a plurality of data signals, the data signal having a duty cycle, the positive signal and the negative signal having the duty cycle of the data signal, the negative signal having a reverse phase to a phase of the positive signal, and to generate a comparison signal based on a comparison of the positive signal and the negative signal; and
a memory device including a plurality of memory chips respectively corresponding to the plurality of duty sensing circuits, each memory chip of the plurality of memory chips respectively configured to generate a data signal of the plurality of data signals, to generate an internal clock signal based on the clock signal, the internal clock signal having a duty cycle, and to correct the duty cycle of the internal clock signal based on the comparison signal.